Product Applications Engineer (NCG 2026)

Summary

Astera Labs provides rack-scale AI infrastructure through connectivity solutions. They are seeking a Firmware Product Application Engineer to assist with firmware engineering and customer engagement, focusing on Leo CXL Smart Memory Controllers and providing technical guidance to customers.

Responsibilities

• Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
• Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
• Assist with end-to-end firmware validation of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning
• Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to help deliver firmware releases and customer collateral on schedule
• Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
• Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral

Skills

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately
• Proficiency in C for embedded firmware development in RTOS environments
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Knowledge of developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences
• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus

Qualifications

Must Haves

• Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
• Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
• Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
• Authorized to work in the US and available to start immediately
• Proficiency in C for embedded firmware development in RTOS environments
• Proficiency in Python for scripting, test automation, and diagnostic tooling
• Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
• Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
• Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
• Knowledge of developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines
• Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences

Nice to Haves

• Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
• Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
• Knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
• Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
• Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
• Experience with server memory performance tuning — latency and bandwidth optimization
• Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus