Compiler Engineer - Algorithmic Workloads Compilation

Summary

Mythic is building the future of AI computing with breakthrough analog technology. The role involves designing compiler IRs and strategies to support algorithmic workloads, collaborating with hardware engineers, and optimizing algorithms for deployment.

Responsibilities

• Extend compiler IRs to represent algorithms not easily captured in DNN graphs including control flow and iterative computation
• Develop compilation strategies that unify analog compute with digital subsystems while maintaining performance and correctness
• Prototype and optimize algorithms with irregular or dynamic control flow in compiler IRs, applying techniques such as vectorization, predication, and scheduling
• Collaborate with hardware engineers to co-design ISA and features that improve support for algorithmic workloads
• Define a roadmap for higher-level programming abstractions that simplify prototyping and accelerate deployment

Skills

• 3+ years of professional experience in compilers or high-performance systems software
• Proficiency in modern C++ (C++14/17/20) and Python
• Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures
• Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)
• Hands-on experience developing MLIR or LLVM dialects for control flow (e.g. scf, cf) or affine/polyhedral representations
• Background in compiler-hardware co-design: working with hardware designers to refine ISA or execution models for efficiency
• Proven ability to prototype irregular or control-flow algorithms in compiler IRs and optimize them for performance and resource constraints
• Experience extending ML compiler stacks (ONNX, IREE, XLA, PyTorch, TVM) to support workloads beyond DNNs

Qualifications

Must Haves

• 3+ years of professional experience in compilers or high-performance systems software
• Proficiency in modern C++ (C++14/17/20) and Python
• Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures
• Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)

Nice to Haves

• Hands-on experience developing MLIR or LLVM dialects for control flow (e.g. scf, cf) or affine/polyhedral representations
• Background in compiler-hardware co-design: working with hardware designers to refine ISA or execution models for efficiency
• Proven ability to prototype irregular or control-flow algorithms in compiler IRs and optimize them for performance and resource constraints
• Experience extending ML compiler stacks (ONNX, IREE, XLA, PyTorch, TVM) to support workloads beyond DNNs

Benefits

• Equity
• Benefits package