Analog IC Design and Verification Engineer

Team Description:

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

The engineer will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. Other responsibilities include:

• Design analog circuit building blocks and subsystems in transistor-level to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top-level specifications
• Works with layout teams to oversee block-level layout of multiple blocks
• Planning and execution of analog verification plan for portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
• Designs, programs, and runs complex tests and reviews tests of junior team members; ensures bugs and other issues are identified and appropriately analyzed
• Consults with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs and goals

Required Qualifications:

• Bachelor of Science degree and additional experience in a related technical field for at least 5 years after receiving the BS degree
• Minimum 5 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
• The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

• Masters or PhD in electrical engineering, physics, or other related fields
• Experience with design for high-volume production
• Experience in lab testing of high-precision analog and mixed-signal ICs
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
• Experience in design and layout with advanced CMOS FinFET technologies
• Skills in scripting and automation for complex simulation scenarios