Ambarella
Verified live 23h ago
Sr. ASIC Design Engineer
Brief overview
US HeadquartersIn-person
MastersOr in progress
$135k–$170k/yrStated range
63 H-1B approvalsDept. of Labor
27 green cardsCertified filings
System VerilogVerilogPythonPerlRTL synthesisTiming optimizationPower optimizationArea optimizationMicro-architecture explorationScriptingAssembly language programmingDesign verificationFunctional coverageCode coverage analysisChip bring-upTest environment development
About the company
Ambarellaambarella.com
Provides video processing and computer vision solutions for autonomous and smart devices.
Visa sponsorship history
4 years sponsoring, last filed FY2026H-1B dependent
Data powered by U.S. Department of Labor. This does not guarantee sponsorship for this specific role.63H-1B approved
95%approval rate
19new H-1B hires
27PERM certified
$150,000median wage / yr
H-1B Petition ApprovalsVisas USCIS actually granted: the strongest sign the company sponsors.
202315
202424
202521
20263
LCA Certified ApplicationsAn early filing step, not a visa approval: it signals intent, not confirmed sponsorship.
20236
20261
Green Card (PERM) FilingsCertified green card filings: a long-term commitment to international hires.
20234
20246
202517
Top sponsored roles
Algorithm EngineerSr. Application EngineerSoftware EngineerBig Data Engineer IIStaff DFT Engineer
Sponsored employees from
ChinaTaiwanSingaporeItalyIndia
Job description
AI Vision Processors For Edge Applications
Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.
Job Description
Position Responsibilities:
- Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference—alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.
- Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
- Synthesize and optimize RTL for timing, area, and power.
- Explore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc.
- Developing unit level test environments and tests cases
- Developing front-end methodologies and tool flows.
- Participating in chip bring-up and testing.
- Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.
Requirements:
- Master’s degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.
- Good understanding of computer architecture, logic design and VLSI design.
- Knowledge of System Verilog, Verilog, python, and Perl.
- Knowledge of design verification, and functional coverage.
- Ability to program in scripting languages and the ability to write assembly language programs.
- Strong communication skills and a good team player.
- Adept problem-solving abilities
- Knowledge of logic synthesis and timing closer is a plus
The base salary range is $135,000 - $170,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
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