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Jane Street
Posted 146 days agoVerified live 2d ago

ASIC Physical Design Engineer

Brief overview

New York, New York, United StatesIn-person
8+ yrsMinimum
153 H-1B approvalsDept. of Labor
53 green cardsCertified filings
Physical design flow ownershipFloor planningPlace and routeTiming closurePhysical verificationPower analysisRTL design and implementationSoftware engineering for hardware development

About the company

Jane Street logo
Jane Streetjanestreet.com

Leaders in proprietary trading and technology innovation.

Visa sponsorship history

4 years sponsoring, last filed FY2026

Data powered by U.S. Department of Labor. This does not guarantee sponsorship for this specific role.
153H-1B approved
98%approval rate
93new H-1B hires
53PERM certified
$300,000median wage / yr
H-1B Petition ApprovalsVisas USCIS actually granted: the strongest sign the company sponsors.
202342
202451
202556
20264
LCA Certified ApplicationsAn early filing step, not a visa approval: it signals intent, not confirmed sponsorship.
20239
20247
202514
20269
Green Card (PERM) FilingsCertified green card filings: a long-term commitment to international hires.
20239
202421
202523
Top sponsored roles
Software EngineerTraderProduction EngineerTrading Desk Operations EngineerSOFTWARE ENGINEER
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Job description

About the Position

We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure.

This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. 

If you've spent your career exclusively in PD, this probably isn't the right fit— but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.

We're big believers in the ability of tools to improve the productivity, reliability, and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

  • You have 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
  • You don't need to have optimized every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
  • Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
  • You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

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