ASIC Physical Design Engineer

Summary

Positron AI is building next-generation AI inference accelerators for low-latency, high-throughput large language model inference. The Physical Design Engineer will implement assigned ASIC blocks from floorplanning through tapeout, debug implementation flows, support timing and signoff closure, automate tasks, and collaborate with cross-functional design teams.

Responsibilities

• Implement assigned blocks through floorplanning, macro placement, and power planning, with guidance from senior engineers
• Run clock tree synthesis, place and route, and routing optimization, and work toward timing closure on your blocks
• Support signal integrity, IR/EM analysis, ECO implementation, and metal fill to help deliver signoff-quality results
• Contribute to tapeout signoff activities for your blocks
• Help maintain and improve flows for power grids, power/ground tiles, and bump planning
• Run congestion analysis and wire estimation to support floorplan decisions
• Learn and apply hierarchical implementation and partitioning strategies on multi-block designs
• Run and debug Innovus-based implementation flows
• Build hands-on experience with tools such as Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre
• Write Tcl and Python scripts to automate tasks, parse reports, and improve team productivity
• Analyze and fix issues across timing, power, area, congestion, DRC, LVS, EM, and IR for your blocks
• Work with backend design services partners on block-level execution
• Take part in implementation reviews, present your results, and incorporate feedback
• Use AI-enabled tools to support QoR analysis, congestion prediction, routing prediction, and floorplan optimization

Skills

• BS/MS in EE/CE (or related field) with 0–3 years of physical design experience (internships and relevant graduate research count)
• Understanding of the physical design flow, including floorplanning, placement, clock tree synthesis, routing, and timing closure
• Working knowledge of static timing analysis concepts (setup/hold, clock skew, timing constraints)
• Exposure to at least one major implementation tool (Innovus, ICC2, or equivalent) from industry or academic projects
• Familiarity with physical verification concepts such as DRC and LVS
• Scripting ability in Tcl, Python, or similar
• Strong problem-solving skills, eagerness to learn, and clear communication
• Currently authorized to work in the U.S
• We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates
• Experience on an advanced-node or academic tapeout
• Exposure to IR drop, EM, or signal integrity analysis
• Coursework or project experience in VLSI design, computer architecture, or AI accelerators
• Familiarity with large SRAM arrays, SerDes, or LPDDR interfaces
• Interest in chiplet architectures and 2.5D advanced packaging

Qualifications

Must Haves

• BS/MS in EE/CE (or related field) with 0–3 years of physical design experience (internships and relevant graduate research count)
• Understanding of the physical design flow, including floorplanning, placement, clock tree synthesis, routing, and timing closure
• Working knowledge of static timing analysis concepts (setup/hold, clock skew, timing constraints)
• Exposure to at least one major implementation tool (Innovus, ICC2, or equivalent) from industry or academic projects
• Familiarity with physical verification concepts such as DRC and LVS
• Scripting ability in Tcl, Python, or similar
• Strong problem-solving skills, eagerness to learn, and clear communication
• currently authorized to work in the U.S
• We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates

Nice to Haves

• Experience on an advanced-node or academic tapeout
• Exposure to IR drop, EM, or signal integrity analysis
• Coursework or project experience in VLSI design, computer architecture, or AI accelerators
• Familiarity with large SRAM arrays, SerDes, or LPDDR interfaces
• Interest in chiplet architectures and 2.5D advanced packaging

Benefits

• This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available
• Unlimited paid time off, so you can truly unplug and recharge
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup
• Equity
• 401(k) with company matching, eligible from day one