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WD
Posted 84 days agoVerified live 8h ago

EDA- CAD Engineer

Brief overview

San Jose, CAIn-person
UndergradOr in progress
$146k–$194k/yrStated range
414 H-1B approvalsDept. of Labor
115 green cardsCertified filings

About the company

For more than 55 years, WD has built the storage infrastructure that powers the world’s data.

Visa sponsorship history

4 years sponsoring, last filed FY2026

Data powered by U.S. Department of Labor. This does not guarantee sponsorship for this specific role.
414H-1B approved
99%approval rate
125new H-1B hires
115PERM certified
$144,664median wage / yr
H-1B Petition ApprovalsVisas USCIS actually granted: the strongest sign the company sponsors.
2023149
2024165
202576
202624
LCA Certified ApplicationsAn early filing step, not a visa approval: it signals intent, not confirmed sponsorship.
2023103
202493
202577
202614
Green Card (PERM) FilingsCertified green card filings: a long-term commitment to international hires.
202354
202417
202534
202610
Top sponsored roles
Staff Engineer, Hardware Development EngineeringSenior Engineer, Industrial EngineeringPrincipal Engineer, Hardware Development EngineeringPrincipal Engineer, R&D EngineeringStaff Engineer, Development Engineering
Sponsored employees from
IndiaChinaSouth KoreaIsraelTaiwan

Job description

Summary

WD is building the infrastructure behind the AI-driven data economy. They are seeking a full-time Electronic Design Automation (EDA) CAD Engineer to develop and commercialize strategic radiation hardened memory technology, while managing CAD flows, automating design tasks, and integrating industry-standard tools.

Responsibilities

  • Design, implement, and maintain robust CAD flows and methodologies for analog and mixed-signal IC design (spanning simulation, physical design, verification and familiarity with RTL/synthesis)
  • Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks
  • Develop custom scripts and internal utilities to automate repetitive design tasks, improve tool interoperability, and maximize engineering efficiency
  • Install, configure, and integrate industry-standard EDA tools (Cadence, Synopsys, Siemens/Mentor Graphics) into our infrastructure
  • Provide technical support to the design teams
  • Monitor and optimize compute resource utilization, license usage, and disk space
  • Troubleshoot design flow bottlenecks, license issues, and tool crashes
  • Act as the primary technical liaison with EDA tool vendors to resolve software bugs, evaluate new features, and manage license compliance
  • Maintain design data management (revision control) systems and ensure clean, reproducible workspace environments
  • Coordination of a Split-Fab Design environment for WD PDKs (for Memory Array Layers) and a CMOS Foundry PDK (for Operational Circuitry)
  • Development of EDA Tool Design Rules for WD’s Memory Array Layers
  • Defining and executing the split-fab tape out flow

Skills

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Minimum 0-5+ years of experience in an EDA CAD engineering or design flow automation role
  • Hands-on experience with industry-standard tools
  • Strong understanding of modern semiconductor manufacturing processes and physical design rules
  • Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A
  • Strong proficiency in scripting languages such as Python, Tcl, Perl, or Shell scripting (bash/csh)
  • Strong working knowledge of Linux/Unix environments, compute grid/scheduler management (e.g., LSF, Slurm, Grid Engine), and version control systems (e.g., Git, Perforce)

Qualifications

Must Haves

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Minimum 0-5+ years of experience in an EDA CAD engineering or design flow automation role
  • Hands-on experience with industry-standard tools
  • Strong understanding of modern semiconductor manufacturing processes and physical design rules
  • Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A
  • Strong proficiency in scripting languages such as Python, Tcl, Perl, or Shell scripting (bash/csh)
  • Strong working knowledge of Linux/Unix environments, compute grid/scheduler management (e.g., LSF, Slurm, Grid Engine), and version control systems (e.g., Git, Perforce)

Benefits

  • Bonuses under either WD’s Short Term Incentive Plan (“STI Plan”) or the Sales Incentive Plan (“SIP”) which provides incentive awards based on Company and individual performance, depending on your role and your performance
  • Annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan
  • RSU awards are also available to eligible new hires, subject to WD's Standard Terms and Conditions for Restricted Stock Unit Awards
  • Paid vacation time
  • Paid sick leave
  • Medical/dental/vision insurance
  • Life, accident and disability insurance
  • Tax-advantaged flexible spending and health savings accounts
  • Employee assistance program
  • Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
  • Tuition reimbursement
  • Transit
  • The Applause Program
  • Employee stock purchase plan
  • The WD Savings 401(k) Plan

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