DFT Engineer

Summary

Ambarella is a worldwide leader in edge AI semiconductors and software. The DFT Engineer will implement, verify, and optimize design-for-test features for complex Computer Vision SoCs, develop scan and memory built-in self-test patterns, and support automated test equipment and silicon production activities.

Responsibilities

• DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post-Production for complex multi-million gate Computer Vision SoC
• Analyze clocking scheme and implement clock control structure for at-speed scan testing
• Develop/Generate high-quality scan and mbist patterns
• DFT Verification (including post place-and-route timing simulations)
• Work with Product Engineering team to bring up scan & mbist patterns on ATE
• Support silicon production activities including failure diagnosis and test optimization

Skills

• MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation
• Knowledge of DFT fundamentals
• Knowledge of Logic design and timing
• Knowledge of Verilog and Python
• Knowledge of Mentor Tessent tools is a plus
• Knowledge of scan diagnostics is a plus

Qualifications

Must Haves

• MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation
• Knowledge of DFT fundamentals
• Knowledge of Logic design and timing
• Knowledge of Verilog and Python

Nice to Haves

• Knowledge of Mentor Tessent tools is a plus
• Knowledge of scan diagnostics is a plus

Benefits

• Opportunity to convert to a full-time regular position
• New-hire RSU grants
• Opportunity for annual RSU grants
• Other highly competitive benefits