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Apple
Posted 3 days agoVerified live 1d ago

FE Engineer

Brief overview

Remote
MastersOr in progress
$150k–$225k/yrStated range
3+ yrsMinimum
6,752 H-1B approvalsDept. of Labor
3,817 green cardsCertified filings
SystemVerilogVerilogRTL DesignPythonPerlTCLComputer ArchitectureDigital Logic DesignConstrained-Random VerificationFunctional and Code CoverageAssertion-Based VerificationPhysical Design and Verification

About the company

Apple is a technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.

Visa sponsorship history

4 years sponsoring, last filed FY2026

Data powered by U.S. Department of Labor. This does not guarantee sponsorship for this specific role.
6,752H-1B approved
98%approval rate
2,551new H-1B hires
3,817PERM certified
$178,006median wage / yr
H-1B Petition ApprovalsVisas USCIS actually granted: the strongest sign the company sponsors.
20231,940
20241,811
20252,018
2026983
LCA Certified ApplicationsAn early filing step, not a visa approval: it signals intent, not confirmed sponsorship.
2023884
20241,000
20251,480
20261,175
Green Card (PERM) FilingsCertified green card filings: a long-term commitment to international hires.
20231,199
20241,386
20251,224
20268
Top sponsored roles
Software Engineering ApplicationsSoftware Development EngineeringSoftware Development EngineerSoftware Engineering SystemsSoftware Development Engineer - Applications
Sponsored employees from
IndiaChinaCanadaTaiwanUnited Kingdom

Job description

Summary

Apple creates consumer technology products and experiences through the collaboration of people and ideas. The FE Engineer will design and develop hardware for Apple’s mobile devices, focusing on CPU micro-architecture, RTL development, functional debugging, and timing and power closure. The role also involves evaluating CPU features and preparing design specification documentation.

Responsibilities

  • Design and develop hardware for Apple’s mobile devices
  • Evaluate new ideas and features for the Central Processing Unit (CPU) hardware
  • Define the Micro-architecture of the CPU hardware
  • Develop the CPU hardware using a Hardware-Description-Language
  • Perform functional debug and closure of the design
  • Responsible for timing and power closure of the design for the target Frequency and Power
  • Prepare documentation of the Design Specification

Skills

  • Master's degree or foreign equivalent in Electrical and Computer Engineering or related field
  • Utilizing System Verilog or Verilog to write RTL for high-speed communication IPs
  • Experience in RTL design utilizing System Verilog or Verilog with complex FSMs, and power saving features
  • Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models
  • Experience in computer architecture and logic design of industry standard interfaces
  • Experience in digital logic design principles and computer architecture concepts including cache coherence and hardware-software interactions
  • Constrained random verification process, functional coverage, code coverage, assertion methodology and philosophy
  • Experience with placement, clock tree synthesis, routing or physical verification using tools from Cadence or Synopsys
  • Experience in debugging complex hardware, including identifying RTL bugs from Verilog code, analyzing simulation failures and fixing issues related to timing or power
  • Understanding of device physics in sub-micron nodes to address issues for leakage power, signal integrity and process variations
  • Experience in handling complex data path logic (MUX trees, adder, comb logic) to meeting timing, performance, area and power goals

Qualifications

Must Haves

  • Master's degree or foreign equivalent in Electrical and Computer Engineering or related field
  • Utilizing System Verilog or Verilog to write RTL for high-speed communication IPs
  • Experience in RTL design utilizing System Verilog or Verilog with complex FSMs, and power saving features
  • Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models
  • Experience in computer architecture and logic design of industry standard interfaces
  • Experience in digital logic design principles and computer architecture concepts including cache coherence and hardware-software interactions
  • Constrained random verification process, functional coverage, code coverage, assertion methodology and philosophy
  • Experience with placement, clock tree synthesis, routing or physical verification using tools from Cadence or Synopsys
  • Experience in debugging complex hardware, including identifying RTL bugs from Verilog code, analyzing simulation failures and fixing issues related to timing or power
  • Understanding of device physics in sub-micron nodes to address issues for leakage power, signal integrity and process variations
  • Experience in handling complex data path logic (MUX trees, adder, comb logic) to meeting timing, performance, area and power goals

Benefits

  • Opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
  • Eligibility for discretionary restricted stock unit awards
  • Ability to purchase Apple stock at a discount through voluntary participation in Apple’s Employee Stock Purchase Plan
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • A range of discounted products and free services
  • For formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition
  • This role might be eligible for discretionary bonuses or commission payments
  • This role might be eligible for relocation

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