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Apple
Posted 3 days agoVerified live 18h ago

Physical Design Engineer

Brief overview

Remote
MastersOr in progress
$174k–$195k/yrStated range
3+ yrsMinimum
6,752 H-1B approvalsDept. of Labor
3,817 green cardsCertified filings
Physical Design for SoCsPlace and Route (PnR)IC Compiler (ICC/ICC2)InnovusFloorplanningClock OptimizationRoutingTiming Analysis and ClosureSynopsys PrimeTimeTiming ECO GenerationTCLPerlPythonUnix ScriptingEMIR AnalysisVoltusRedHawk

About the company

Apple is a technology company that designs, manufactures, and markets consumer electronics, personal computers, and software.

Visa sponsorship history

4 years sponsoring, last filed FY2026

Data powered by U.S. Department of Labor. This does not guarantee sponsorship for this specific role.
6,752H-1B approved
98%approval rate
2,551new H-1B hires
3,817PERM certified
$178,006median wage / yr
H-1B Petition ApprovalsVisas USCIS actually granted: the strongest sign the company sponsors.
20231,940
20241,811
20252,018
2026983
LCA Certified ApplicationsAn early filing step, not a visa approval: it signals intent, not confirmed sponsorship.
2023884
20241,000
20251,480
20261,175
Green Card (PERM) FilingsCertified green card filings: a long-term commitment to international hires.
20231,199
20241,386
20251,224
20268
Top sponsored roles
Software Engineering ApplicationsSoftware Development EngineeringSoftware Development EngineerSoftware Engineering SystemsSoftware Development Engineer - Applications
Sponsored employees from
IndiaChinaCanadaTaiwanUnited Kingdom

Job description

Summary

Apple develops consumer technology products and experiences, and is seeking a Physical Design Engineer to support physical implementation and timing closure for core platforms and SoCs. The role involves collaborating with logic design teams, completing netlist-to-GDS2 implementation, performing verification and signoff, resolving design issues, and optimizing power, performance, and area.

Responsibilities

  • Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle
  • Complete the net list to GDS2 implementation for partition(s), meeting schedule and design goals
  • Perform timing, physical, and electrical verification, and driving signoff closure for the partitions
  • Generate and implement ECOs to rectify timing, noise, and EM IR violations
  • Resolve design and flow issues related to physical design, while identifying potential solutions and driving execution
  • Drive optimization of PnR partitions to achieve the best Power/Performance/Area
  • Streamline the timing signoff criteria, timing analysis methodologies, and flows (critical path spice simulation), and develop/enhance auto ECO generation scripts for timing closure
  • Responsible for hands-on physical implementation and timing closure of core platforms and Socs

Skills

  • Master's degree or foreign equivalent in Electrical and Computer Engineering, or related field
  • Utilizing PNR tools like ICC / ICC2 / Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs
  • Utilizing timing analysis tools like Synopsys PrimeTime to be used for timing analysis, and timing ECO generation for timing closure of partitions on SoCs
  • Utilizing TCL / Perl / Python and Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure
  • Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs
  • Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs
  • Understanding results from EMIR analysis tools like Voltus or Redhawk and generating fixes to address violations or improve QoR
  • Understanding results from Physical verification tools like calibre and generating fixes to address violations

Qualifications

Must Haves

  • Master's degree or foreign equivalent in Electrical and Computer Engineering, or related field
  • Utilizing PNR tools like ICC / ICC2 / Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs
  • Utilizing timing analysis tools like Synopsys PrimeTime to be used for timing analysis, and timing ECO generation for timing closure of partitions on SoCs
  • Utilizing TCL / Perl / Python and Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure
  • Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs
  • Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs
  • Understanding results from EMIR analysis tools like Voltus or Redhawk and generating fixes to address violations or improve QoR
  • Understanding results from Physical verification tools like calibre and generating fixes to address violations

Benefits

  • Opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
  • Eligibility for discretionary restricted stock unit awards
  • Ability to purchase Apple stock at a discount through Apple’s Employee Stock Purchase Plan, if voluntarily participating
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • A range of discounted products and free services
  • Reimbursement for certain educational expenses, including tuition, for formal education related to advancing your career at Apple
  • This role might be eligible for discretionary bonuses or commission payments
  • This role might be eligible for relocation

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