ASIC Design Engineer

Summary

Positron AI is building next-generation AI inference accelerators and custom ASIC systems for low-latency, high-throughput large language model inference. The ASIC Design Engineer will design, implement, and deliver IP blocks and subsystems for inference ASICs and SoCs, writing and verifying SystemVerilog RTL while learning the front-end flow from microarchitecture through RTL signoff. The role also involves collaborating with architecture, verification, and physical design teams and developing toward greater technical ownership.

Responsibilities

• Implement clean, parameterized SystemVerilog RTL for assigned blocks based on microarchitecture specs developed with senior engineers
• Contribute to microarchitecture documentation and help define block-level interfaces
• Add embedded assertions and follow team guidelines for clocking, resets, and power intent
• Run and debug lint, CDC/RDC, and synthesis checks on your blocks, and resolve issues with support from the team
• Help with timing analysis and work with PD on block-level timing fixes
• Track and report PPA metrics for your blocks, and propose optimizations
• Support integration of standard interfaces and IP (e.g., AMBA AXI, DMA engines, memory controllers)
• Learn and apply protocol requirements for high-performance interconnects and memory interfaces
• Follow established coding guidelines, IP packaging standards, and signoff checklists
• Write and maintain scripts (Python/Tcl/Make) that improve design flows and team productivity
• Work with Verification to review test plans, debug failures, and close coverage on your blocks
• Help correlate RTL behavior against architecture and performance models
• Take part in bring-up and post-silicon debug activities as needed
• Take part in design reviews, present your work, and incorporate feedback
• Build expertise in microarchitecture tradeoffs through mentorship from senior engineers

Skills

• BS/MS in EE/CE (or related field) with 0–3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count)
• Solid working knowledge of SystemVerilog/Verilog for synthesizable RTL design
• Understanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing
• Exposure to front-end tools and flows (simulation, lint, synthesis, or STA) from industry or academic projects
• Familiarity with at least one of: AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design
• Scripting ability in Python, Tcl, or similar
• Strong problem-solving skills, eagerness to learn, and clear written and verbal communication
• Coursework, research, or project experience in computer architecture or AI/ML accelerator design (matrix/vector engines, systolic arrays)
• Experience writing SystemVerilog Assertions (SVA) or exposure to formal verification
• Familiarity with low-power design concepts (clock gating, power gating, UPF)
• Experience with cocotb or UVM testbenches
• Exposure to RISC-V, FPGA prototyping, or tapeout of a chip (including academic tapeouts)

Qualifications

Must Haves

• BS/MS in EE/CE (or related field) with 0–3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count)
• Solid working knowledge of SystemVerilog/Verilog for synthesizable RTL design
• Understanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing
• Exposure to front-end tools and flows (simulation, lint, synthesis, or STA) from industry or academic projects
• Familiarity with at least one of: AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design
• Scripting ability in Python, Tcl, or similar
• Strong problem-solving skills, eagerness to learn, and clear written and verbal communication

Nice to Haves

• Coursework, research, or project experience in computer architecture or AI/ML accelerator design (matrix/vector engines, systolic arrays)
• Experience writing SystemVerilog Assertions (SVA) or exposure to formal verification
• Familiarity with low-power design concepts (clock gating, power gating, UPF)
• Experience with cocotb or UVM testbenches
• Exposure to RISC-V, FPGA prototyping, or tapeout of a chip (including academic tapeouts)

Benefits

• Equity
• Comprehensive benefits
• Flexible work environment
• Clear opportunities to grow your scope, skills, and influence as the company scales
• Get hands-on ownership of real silicon blocks early in your career
• Learn directly from experienced ASIC architects and designers
• Mentorship from senior engineers